? 2005 fairchild semiconductor corporation ds009917 www.fairchildsemi.com november 1988 revised february 2005 74ac14 ? 74act14 hex inverter with schmitt trigger input 74ac14 74act14 hex inverter with schmitt trigger input general description the 74ac14 and 74act14 contain six inverter gates each with a schmitt trigger input. they are capable of transform- ing slowly changing input signals into sharply defined, jitter- free output signals. in addition, they have a greater noise margin than conventional inverters. the 74ac14 and 74act14 have hysteresis between the positive-going and negative-going input thresholds (typi- cally 1.0v) which is determined internally by transistor ratios and is essentially insensitive to temperature and sup- ply voltage variations. features i cc reduced by 50% outputs source/sink 24 ma 74act14 has ttl-compatible inputs ordering code: device also available in tape and reel. specify by appending suffix letter ?x? to the ordering code. pb-free package per jedec j-std-020b. note 1: ?_nl? indicates pb-free package (per jedec j-std-020b). device available in tape and reel only. fact is a trademark of fairchild semiconductor corporation. order number package package description number 74ac14sc m14a 14-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow 74ac14scx_nl (note 1) m14a pb-free 14-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow 74ac14sj m14d pb-free 14-lead small outline package (sop), eiaj type ii, 5.3mm wide 74AC14MTC mtc14 14-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74AC14MTCx_nl (note 1) mtc14 pb-free 14-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74ac14pc n14a 14-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide 74act14sc m14a 14-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow 74act14mtc mtc14 14-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74act14mtcx_nl (note 1) mtc14 pb-free 14-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74act14pc n14a 14-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide
www.fairchildsemi.com 2 74ac14 74act14 logic symbol ieee/iec pin descriptions connection diagram function table pin names description i n inputs o n outputs input output ao lh hl
3 www.fairchildsemi.com 74ac14 74act14 absolute maximum ratings (note 2) recommended operating conditions note 2: absolute maximum ratings are those values beyond which damage to the device may occur. the databook specifications should be met, with- out exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. fairchild does not recommend operation of fact circuits outside databook specifications. dc electrical characteristics for ac note 3: all outputs loaded; thresholds on input associated with output under test. note 4: maximum test duration 2.0 ms, one output loaded at a time. note 5: i in and i cc @ 3.0v are guaranteed to be less than or equal to the respective limit @ 5.5v v cc . supply voltage (v cc ) 0.5v to 7.0v dc input diode current (i ik ) v i 0.5v 20 ma v i v cc 0.5v 20 ma dc input voltage (v i ) 0.5v to v cc 0.5v dc output diode current (i ok ) v o 0.5v 20 ma v o v cc 0.5v 20 ma dc output voltage (v o ) 0.5v to v cc 0.5v dc output source or sink current (i o ) r 50 ma dc v cc or ground current per output pin (i cc or i gnd ) r 50 ma storage temperature (t stg ) 65 q c to 150 q c junction temperature (t j ) pdip 140 q c supply voltage (v cc ) ac 2.0v to 6.0v act 4.5v to 5.5v input voltage (v i )0v to v cc output voltage (v o )0v to v cc operating temperature (t a ) 40 q c to 85 q c symbol parameter v cc t a 25 q ct a 40 q c to 85 q c units conditions (v) typ guaranteed limits v oh minimum high level 3.0 2.99 2.9 2.9 v i out 50 p a output voltage 4.5 4.49 4.4 4.4 5.55.495.4 5.4 3.0 2.56 2.46 v i oh 12 4.5 3.86 3.76 i oh 24 ma 5.5 4.86 4.76 i oh 24 ma (note 3) v ol maximum low level 3.0 0.002 0.1 0.1 v i out 50 p a output voltage 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 3.0 0.36 0.44 v i ol 12 4.5 0.36 0.44 i ol 24 ma 5.5 0.36 0.44 i ol 24 ma (note 3) i in (note 5) maximum input leakage current 5.5 r 0.1 r 1.0 p av i v cc , gnd v t maximum positive 3.0 2.2 2.2 t a worst case threshold 4.5 3.2 3.2 v 5.5 3.9 3.9 v t minimum negative 3.0 0.5 0.5 t a worst case threshold 4.5 0.9 0.9 v 5.5 1.1 1.1 v h(max) maximum hysteresis 3.0 1.2 1.2 t a worst case 4.5 1.4 1.4 v 5.5 1.6 1.6 v h(min) minimum hysteresis 3.0 0.3 0.3 t a worst case 4.5 0.4 0.4 v 5.5 0.5 0.5 i old minimum dynamic 5.5 75 ma v old 1.65v max i ohd output current (note 4) 5.5 75 ma v ohd 3.85v min i cc maximum quiescent 5.5 2.0 20.0 p av in v cc (note 5) supply current or gnd
www.fairchildsemi.com 4 74ac14 74act14 ac electrical characteristics for ac note 6: voltage range 3.3 is 3.3v r 0.3v voltage range 5.0 is 5.0v r 0.5v dc electrical characteristics for act note 7: all outputs loaded; thresholds on input associated with output under test. note 8: maximum test duration 2.0 ms, one output loaded at a time. symbol parameter v cc t a 25 q ct a 40 q c to 85 q c units (v) c l 50 pf c l 50 pf (note 6) min typ max min max t plh propagation delay 3.3 1.5 9.5 13.5 1.5 15.0 ns 5.0 1.5 7.0 10.0 1.5 11.0 t phl propagation delay 3.3 1.5 7.5 11.5 1.5 13.0 ns 5.01.56.08.51.59.5 symbol parameter v cc t a 25 q ct a 40 q c to 85 q c units conditions (v) typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out 0.1v input voltage 5.5 1.5 2.0 2.0 or v cc 0.1v v il maximum low level 4.5 1.5 0.8 0.8 v v out 0.1v output voltage 5.5 1.5 0.8 0.8 or v cc 0.1v v oh minimum high level 4.5 4.49 434 4.4 v i out 50 p a output voltage 5.5 5.49 5.4 5.4 v v in v il or v ih 4.5 3.86 3.76 i oh 24 ma 5.5 4.86 4.76 i oh 24 ma (note 7) v ol maximum low level 4.5 0.001 0.1 0.1 v i out 50 p a output voltage 5.5 0.001 0.1 0.1 v v in v il or v ih 4.5 0.36 0.44 i ol 24 ma 5.5 0.36 0.44 i ol 24 ma (note 7) i in maximum input leakage current 5.5 r 0.1 r 1.0 p av i v cc , gnd v h(max) maximum hysteresis 4.5 1.4 1.4 v t a worst case 5.5 1.6 1.6 v h(min) minimum hysteresis 4.5 0.4 0.4 v t a worst case 5.5 0.5 0.5 v t maximum positive 4.5 2.0 2.0 v t a worst case threshold 5.5 2.0 2.0 v t minimum negative 4.5 0.8 0.8 v t a worst case threshold 5.5 0.8 0.8 i cct maximum i cc /input 5.5 0.6 1.5 ma v i v cc 2.1v i old minimum dynamic 5.5 75 ma v old 1.65v max i ohd output current (note 8) 5.5 75 ma v ohd 3.85v min i cc maximum quiescent 5.5 2.0 20.0 p av in v cc supply current or gnd
5 www.fairchildsemi.com 74ac14 74act14 ac electrical characteristics for act note 9: voltage range 5.0 is 5.0v r 0.5v capacitance symbol parameter v cc t a 25 q ct a 40 q c to 85 q c units (v) c l 50 pf c l 50 pf (note 9) min typ max min max t plh propagation delay 5.0 3.0 8.0 10.0 3.0 11.0 ns data to output t phl propagation delay 5.0 3.0 8.0 10.0 3.0 11.0 ns data to output symbol parameter typ units conditions c in input capacitance 4.5 pf v cc open c pd power dissipation capacitance for ac 25.0 pf v cc 5.0v for act 80
www.fairchildsemi.com 6 74ac14 74act14 physical dimensions inches (millimeters) unless otherwise noted 14-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow package number m14a
7 www.fairchildsemi.com 74ac14 74act14 physical dimensions inches (millimeters) unless otherwise noted (continued) pb-free 14-lead small outline package (sop), eiaj type ii, 5.3mm wide package number m14d
www.fairchildsemi.com 8 74ac14 74act14 physical dimensions inches (millimeters) unless otherwise noted (continued) 14-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide package number mtc14
9 www.fairchildsemi.com 74ac14 74act14 hex inverter with schmitt trigger input physical dimensions inches (millimeters) unless otherwise noted (continued) 14-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide package number n14a fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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